The invention is generally related to the field of fabricating copper interconnects in semiconductor devices and more specifically to a reducing copper line resistivity.
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects due to the significantly lowered resistivity of copper versus aluminum. The resistivity of copper is less than 1.8 xcexcxcexa9-cm for copper lines wider than 0.5 xcexcm in linewidth. However, the value increases rapidly as the copper line/via dimension decreases. At 0.20 xcexcm linewidth, the copper line resistivity was measured to be 2.15 xcexcxcexa9-cm. The increase in copper resistivity is expected to accelerate as the dimension continues to shrink. Simulations indicate that the copper resistivity will surpass aluminum resistivity of 2.8 xcexcxcexa9-cm at the 0.08 xcexcm technology. FIG. 1 displays the simulation results that show how quickly the resistivity rises as linewidth decreases using current copper interconnect approaches.
The invention reduces copper line resistivity by smoothing trench and via sidewalls. After the via and/or trench etches, the rough sidewalls are smoothed by depositing a thin layer of liner material. If desired, a directional etch may follow the deposition to remove liner material from the horizontal surfaces. Processing continues to form the copper interconnect with any desired barrier layers.
An advantage of the invention is providing a copper interconnect with reduced line resistivity for deep sub-quarter micron devices.